Conventionally, a dynamic RAM, for example, a dynamic RAM with a stacked cell capacitor formed into a cylindrical shape to increase the capacitance, has a memory cell with the structure shown in FIG. 38. A gate oxide film 5 is formed in the element region formed of a field SiO.sub.2 film 2 on p-type silicon substrate 1 and on this a polysilicon word line WL and a SiO.sub.2 layer 6 are formed, then n.sup.+ -type semiconductor regions 3 (source region) and 4 (drain region) are formed by a self-alignment method which masks the word line WL.
Then, a SiO.sub.2 layer 7 for passivation and a Si.sub.3 N.sub.4 layer 8 and a SiO.sub.2 layer 9 for substrate protection are successively formed on the entire surface, a contact hole 10 is formed in one part of the laminated film on n.sup.+ -type source region 3, a polysilicon capacitor electrode 11 (storage node) is formed to include the contact hole 10 and to be connected to source region 3, and a cylindrical shape polysilicon layer 13 is formed on the polysilicon layer 11. Furthermore, a dielectric film, for example, Si.sub.3 N.sub.4 film 15 is deposited on the entire surface and an upper capacitor electrode (plate electrode) composed of polysilicon layer 16 is formed on the Si.sub.3 N.sub.4 film.
It is thus formed into a structure in which capacitor Cap with capacitance expanded by screen type polysilicon layer 13 is connected to source region 3 with the top and bottom electrodes 16 and 11 and dielectric film 15.
Also, a memory cell M-CEL of a dynamic RAM for use in, for example, 16 Mb and 64 Mb memory chips is formed by an interlayer insulation film, for example, a silicate glass (BPSG layer) 36 doped with boron and phosphorus formed on an upper electrode 16 by the CVD method, a contact hole 49 reaching a n.sup.+ -type drain region 4 formed in it, and a bit line BL adhered to contact hole 49 via polysilicon layer 50.
This type of dynamic RAM is generally composed of peripheral circuit part PC and memory cell array part MA having many memory cells M-CEL as shown in FIG. 34 (however, the elements in each part are shown schematically in the fig.). On the memory cell array part MA and peripheral circuit part PC, the BPSG layer 36 is formed by a process to be explained below and wiring such as bit line BL, etc. is provided.
As shown in FIG. 34, many memory cells M-CELL (the cell height is about 1.2 .mu.m, word line space is about 0.4 .mu.m, word line height is about 3500 .ANG.) with associate stack cell capacitor Cap as shown in FIG. 41 are formed in an array in memory cell array part MA on one principal surface of p-type silicon substrate 1, and each MOS transistor TR constituting the input/output circuit is formed in peripheral circuit part PC. These transistors TR are composed of a structure in which polysilicon gate electrode 20 between is provided n.sup.+ -type source region 23 and n.sup.+ -type drain region 24 via gate oxide film 5.
Next, BPSG layer 36 is deposited on the entire surface of substrate 1 in thickness of 0.6 .mu.m by the CVD method as shown in FIG. 35. On the surface of the deposition layer 36, along with concaved gradation 21 created between memory cells M-CELL due to the thickness of word line WL and the screen height of cell capacitor Cap, etc., a gradation steeper 22 than gradation 21 is created between memory cell array part MA and peripheral circuit part PC due to the lack of a high structure like a screen structure on the outside of the terminal part of memory cell array part MA (the distance between gate electrode 20 and word line WL of the memory cell is about 4 .mu.m).
Here gradation 21 in memory cell array part MA is sometimes called a "local gradation" in the specifications of the present application but this is a gradation between multiple word lines WL (or between the cells) which are relatively close, and normally, it is created when the distance between the word lines or between the wiring is less than 10 .mu.m.
Also, gradation 22 between memory cell array part MA and peripheral circuit part PC is sometimes called a "global gradation" in the specifications of the present application but this is quite steep and normally it is created when the distance between the word lines or between the wiring is more than 10 .mu.m (however, in some cases it is less than 10 .mu.m).
Gradation 25 is created on the sides of gate electrode 20 and between gate electrodes 20--20 even in peripheral circuit part PC but in this the height difference is smaller than global gradation 22 (however, a height difference equal to local gradation 21 or greater may be manifested).
These gradations 21, 22, and 25 need to be eliminated and be flattened in order to provide wiring on BPSG layer 36 with reliability. For this, reflow of BPSG layer 36 is executed by annealing for 10 minutes at 900.degree. C. in the state shown in FIG. 35.
However, though local gradations 21 are essentially eliminated, gradation 25 of peripheral circuit part PC becomes a gentle slope like 35, and the steep shape of global gradation 22 becomes a gentle slope as shown in FIG. 36, flattening near global gradation 22 with large height difference is difficult. Namely, gradation 32 (this is also a global gradation) with a height difference of about 1.2 .mu.m is left between memory cell array part MA and peripheral circuit part PC. When contact hole 49 is formed in the prescribed location of BPSG layer 36 and a prescribed wiring, specifically, bit line BL is formed via a polysilicon layer as shown in FIG. 37 in this state, there is a tendency for wiring BL to disconnect and short-circuit during the photolithography since the gradation is great in the location of global gradation 32. Namely, when, for example, positive type photoresist is thickly coated in the disconnected part, exposure is not possible to the bottom part of the photoresist and short-circuit occurs or the unexposed part of the photoresist is exposed by irregular reflection, etc. of light due to the step of gradation 32, the pattern width of the wiring formed by etching with photoresist deforms in a disordered pattern as a mask, and disconnection of the wiring may occur.
When this happens the reliability of the wiring becomes unfavorable, there is a limit to refining the wiring width and pitch, and this is very inconvenient for manufacturing of highly integrated semiconductor devices.
The objective of our invention is to provide a manufacturing method which can execute the flattening of the insulation layer such as the BPSG layer easily and reliably and can apply the wiring, etc. reliably and with a margin for reliability!.